Since simulation tools and FPGA tools use such vastly different inputs to feed in files (🙄 ), we want to leverage FuseSoC’s ability to let us define a “generic” file list that gets mushed into a nice intermediate format that we can then parse in Python to generate filelists for the particular tools

Ideally we’d be able to use FuseSoC’s ability to run all the way through (including simulation and FPGA builds). However, we have some quirks. Testing is cocotb or scary custom DPI based, so there aren’t great FuseSoC bindings. FPGA builds are based on Corundum’s build system, which I don’t feel like porting to FuseSoC. As a result, the quickest way is just to generate filelists.

Overall Design:

• Each protocol tile folder has a core file
• Directories in tcp_hw also kind of arbitrarily have core files
• If you are app, you can depend on these things and also add extra util files that are specific to you.

FuseSoC usage in Beehive:

• So we can’t setup our FuseSoC stuff in the root directory, because then it tries to recursively look for core files in Corundum, and it turns out some symlinks in Corundum form cycles, which is incredibly unhelpful
  • Specifically, when the lib subdirectories, have examples, those often symlink back to lib to get the components, but then you end up in a cycle
• As a result, the way we do it is to setup your fusesoc.conf in the directory you’ve setup to build the overall thing and then add libraries that point to directories under the root of the repo (network_tiles, apps, ect.). This way, FuseSoC will only recursively search the directories that were pointed to as libraries
• We then run just the setup phase of fusesoc run in order to acquire the EDAM file that we can parse. This resolves the dependency chains, so things at the bottom like utils and includes files come first in the filelist, and collects all the files into one file. It also runs generators to preprocess files
• We then have a script (util/scripts/generate_filelist.py) to parse the filelist to find include files mainly. This is because we need +incdir+ for the simulation tools and none of the include files passed as sources, but Vivado requires you to add all the include files as sources and then use some TCL to mark them as Verilog header files
  • The script options are hopefully documented well enough in the help message of the script, but there are 3 options
    • target: do we want the filelist for Corundum’s FPGA flow (corundum_fpga) or do we want a flist (filst)
    • edam_file: what EDAM file from FuseSoC are we parsing? This is probably in build/<system_name_thing>/<target>/<system_name_thing>.eda.yml
    • output_file: what file should we write the output to

Example usage:

• Best example (at the moment) is in cocotb_testing/udp_echo
• Run make init_fusesoc to bring in the other libraries
  • This sets the cache root where the generated files go
  • It also adds a bunch of libraries using fusesoc library add
  • You should only need to run this once on your first build in order to add the libraries.
  • Using fusesoc core list you should see all the cores that things depend on which were found as part of the libraries
• Run make gen_filelist to generate the filelist for cocotb testing.
  • This runs the setup phase of fusesoc in order to acquire the EDAM and generate an flist which can be used with the simulator tools as a COMPILE_ARG of cocotb